LM3481

COMP

FB

AGND

UVLO

DR

PGND

FA/SYNC/SD

1

2

3

4

5

6

7

8

9

10

LM3481

SNVS346E – NOVEMBER 2007 – REVISED APRIL 2012

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

Figure 2. 10-Lead VSSOP Package

(DGS-10 Package)

PIN DESCRIPTIONS

Pin Name

Pin Number

Description

1

Current sense input pin. Voltage generated across an external sense resistor is fed into this pin.

UVLO

2

these resistances determine the input voltage which allows switching and the hysteresis to disable

switching.

COMP

3

Compensation pin. A resistor and capacitor combination connected to this pin provides compensation for

the control loop.

FB

4

Feedback pin. Inverting input of the error amplifier.

AGND

5

Analog ground pin. Internal bias circuitry reference. Should be connected to PGND at a single point.

FA/SYNC/SD

6

Frequency adjust, synchronization, and shutdown pin. A resistor connected from this pin to ground sets the

oscillator frequency. An external clock signal at this pin will synchronize the controller to the frequency of

the clock. A high level on this pin for

≥ 30 µs will turn the device off and the device will then draw 5 µA

from the supply typically.

PGND

7

Power ground pin. External power circuitry reference. Should be connected to AGND at a single point.

DR

8

Drive pin of the IC. The gate of the external MOSFET should be connected to this pin.

9

Driver supply voltage pin. A bypass capacitor must be connected from this pin to PGND. See DRIVER

SUPPLY CAPACITOR SELECTION section.

10

Power supply input pin.

2

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Product Folder Links: LM3481