PixArt Imaging Inc.

PAS6329

CMOS Image Sensor IC

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

11

PixArt Imaging Inc.

V1.0, 2011/03/03

0

9F

159

R_LSC_R1[6:0]

[6:0]

0x00

Quartic parameter of R-channel

0

A0

160

R_LSC_G1[6:0]

[6:0]

0x00

Quartic parameter of G-channel

0

A1

161

R_LSC_B1[6:0]

[6:0]

0x00

Quartic parameter of B-channel

0

A2

162

R_LSC_R2[6:0]

[6:0]

0x50

Square parameter of R-channel

0

A3

163

R_LSC_G2[6:0]

[6:0]

0x50

Square parameter of G-channel

0

A4

164

R_LSC_B2[6:0]

[6:0]

0x50

Square parameter of B-channel

0

A5

165

R_LSFT_1[2:0]

[2:0]

0x04

Reserved

0

A6

166

R_LSFT_2[1:0]

[1:0]

0x00

Reserved

0

A7

167

R_LSFT_3[2:0]

[2:0]

0x02

Reserved

0

AE

174

AWB_Valid__PixCnt_vs[15:8]

[7:0]

0x00

AWB valid pixel cnt (by8)

0

AF

175

AWB_Valid__PixCnt_vs[7:0]

[7:0]

0x00

AWB valid pixel cnt (by8)

0

B0

176

Total_Gain[14:8]

[6:0]

0x00

Total gain (FG * GG, 7.8 format)

0

B1

177

Total_Gain[7:0]

[7:0]

0x00

Total gain (FG * GG, 7.8 format)

0

B2

178

AWB_Sum_R[15:8]

[7:0]

0x00

AWB Sum R

0

B3

179

AWB_Sum_R[7:0]

[7:0]

0x00

AWB Sum R

0

B4

180

AWB_Sum_G[15:8]

[7:0]

0x00

AWB Sum G

0

B5

181

AWB_Sum_G[7:0]

[7:0]

0x00

AWB Sum G

0

B6

182

AWB_Sum_B[15:8]

[7:0]

0x00

AWB Sum B

0

B7

183

AWB_Sum_B[7:0]

[7:0]

0x00

AWB Sum B

0

B8

184

LineCnt_Sensor[7:0]

[7:0]

0x00

Line counter

LineCnt_Sensor[9:8]

[1:0]

0x00

Line counter

0

B9

185

FrameCnt[2:0]

[6:4]

0x00

Frame counter (0~7)

0

BA

186

Ycap8bit

[7:0]

0x00

Y sum report

0

BB

187

AWB_EnH_vs

[6]

0x00

AWB enable sync by vsync

0

BB

187

AE_EnH_vs

[7]

0x00

AE enable sync by vysnc

0

BC

188

AG_stage[7:0]

[7:0]

0x00

AG Stage

0

BD

189

AE_stage[4:0]

[4:0]

0x00

AE Stage

0

BE

190

Reg_lpf[7:0]

[7:0]

0x00

Line Per Frame Register

0

BF

191

Reg_lpf[13:8]

[5:0]

0x00

Line Per Frame Register

0

C0

192

Reg_ny [7:0]

[7:0]

0x00

Ny Register

0

C1

193

Reg_ny [10:8]

[2:0]

0x00

Ny Register

0

C2

194

Reg_ne[7:0]

[7:0]

0x00

Ne Register

0

C3

195

Reg_ne[12:8]

[4:0]

0x00

Ne Register

0

CC

204

DGn_R_vs[7:0]

[7:0]

0x00

R Digital Gain sync by vsync

0

CD

205

DGn_R_vs[8]

[0]

0x00

R Digital Gain sync by vsync

0

CE

206

DGn_G_vs[7:0]

[7:0]

0x00

G Digital Gain sync by vsync

0

CF

207

DGn_G_vs[8]

[0]

0x00

G Digital Gain sync by vsync

0

D0

208

DGn_B_vs[7:0]

[7:0]

0x00

B Digital Gain sync by vsync

0

D1

209

DGn_B_vs[8]

[0]

0x00

B Digital Gain sync by vsync

0

D4

212

reg_FG_stage_6329[7:0]

[7:0]

0x00

AE computed Front gain

reg_cgh_6329[1:0]

[1:0]

0x00

AE computed CGH

0

D5

213

reg_DG_6329[3:0]

[7:4]

0x00

AE computed DG

0

DE

222

AE_Already_Locked_vs

[0]

0x00

1=locked, 0=not locked

0

E0

224

R_ISP_HSize[7:0]

[7:0]

0x80

ISP output Horizontal size, (before skip function)

0

E1

225

R_ISP_HSize[9:8]

[1:0]

0x02

ISP output Horizontal size, (before skip function)

0

E2

226

R_ISP_VSize[7:0]

[7:0]

0xe0

ISP output Vertical size, (before skip function)

0

E3

227

R_ISP_Vsize[9:8]

[1:0]

0x01

ISP output Vertical size, (before skip function)

0

E6

230

R_ISP_FastUpdate

[0]

0x00

ISP Fast Update mode

0

EB

235

R_SwTristate

[0]

0x0

Sw Tristate

ISP_Update

[0]

0x00

ISP_UpdateFlag

0

ED

237

ISP_FrameSkip

[4]

0x00

(ISP_UpdateFlag=1, update)

RegBank_SWRstn

[0]

0x00

SW reset for RegBank0, RegBank1

Sensor_IF_SWRstn

[1]

0x00

SW reset for Sensor interface

ISP_Top1_SWRstn

[2]

0x00

SW reset for ISP_Top1

ISP_Top2_SWRstn

[3]

0x00

SW reset for ISP_Top2

0

EE

238

AE_AWB_SWRstn

[4]

0x00

SW reset for AE_AWB