MPC8347ECVRALFB datasheet(97/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Document Revision History

2/2009

• Added footnote 6 to Table 7.

•In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.

•In Table 39, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock

in DLL bypass mode). Similarly, made the same correction to Figure 22, Figure 24, and Figure 25

for output signals.

• Added footnote 10 and 11 to Table 55 and Table 56.

•In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.

•In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five

independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and

“the four AVDD pins.”

•In Table 58, corrected the max csb_clk to 266 MHz.

•In Table 64, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz

• Added footnote 4 to Table 70.

•In Table 70, updated note 1 to say the following: “For temperature range = C, processor frequency

is limited to 533 (TBGA) and 400 (PBGA) with a platform frequency of 266.”

4/2007

• In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and

added USB to the seventh row.

•In Table 4, “Operating Frequencies for TBGA,” added column for 400 MHz.

•In Section 21.7, “Pull-Up Resistor Requirements,“deleted last two paragraphs and after first

paragraph, added a new paragraph.

• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”

3/2007

• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.

• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to tCISKEW

and deleted original note 3; renumbered the remaining notes.

• In Figure 43, “JTAG Interface Connection,” updated with new figure.

• In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’

row, changed the value in the 533 MHz column to 100-333.

• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK

Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz

CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,

changed the CORE PLL value to 0000110.

• In Section 23, “Ordering Information,” replaced first paragraph and added a note.

• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.

1/2007

• In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency).

• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply

voltage of 1.3 V for 667-MHz parts.

• In Table 4, “MPC8347EA Power Dissipation,” added two footnotes to 667-MHz row showing

nominal core supply voltage of 1.3 V for 667-MHz parts.

• In Table 54, “MPC8347EA (TBGA) Pinout Listing,” updated VDD row to show nominal core supply

voltage of 1.3 V for 667-MHz parts.

12/2006

Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified Tddkhds for 333 MHz

from 900 ps to 775 ps.

11/2006

• Updated note in introduction.

• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA

parts for all silicon revisions, and 400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3.

• In Table 5, “MPC8347EA Typical I/O Power Dissipation,” added GVDD 1.8-V values for DDR2;

added table footnote to designate rates that apply only to the TBGA package.

• In Section 23, “Ordering Information,” replicated note from document introduction.

Table 72. Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

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