REV. B

–20–

AD7722

SERIAL INTERFACE

The AD7722’s serial data interface port allows easy interfacing

to industry-standard digital signal processors. The AD7722

operates solely in the master mode, providing three serial data

output pins for transfer of the conversion results. The serial data

clock output (SCO), serial data output (SDO), and frame sync

output (FSO) are all synchronous with CLKIN. SCO frequency

is always one-half the CLKIN frequency. FSO is continuously

generalized timing diagrams in Figure 2 show how the AD7722

may be used to transmit its conversion results.

Serial data shifts out of the SDO pin synchronous with SCO. The

FSO is used to frame the output data transmission to an external

device. An output data transmission is 32 SCO cycles in duration.

The serial data shifts out of the SDO pin MSB first, LSB last

for a duration of 16 SCO cycles. For the next 16 SCO cycles,

SDO outputs zeros.

Two control inputs, SFMT and CFMT, select the format for the

serial data transmission. FSO is either a pulse (approximately

one SCO cycle in duration) or a square wave with a period of

32 SCO cycles, depending on the state of the SFMT. The logic

level applied to SFMT also determines if the serial data is valid

on the rising or falling edge of the SCO. The clock format pin,

CFMT, simply switches the phase of SCO for the selected

FSO format.

With a logic low level on SFMT and CFMT set low (Figure 4),

FSO pulses high for one SCO cycle at the beginning of a data

transmission frame. When FSO goes low, the MSB is available

on the SDO pin after the rising edge of SCO and can be latched

on the SCO falling edge.

With a logic high level on SFMT and CFMT set low (Figure 4),

the data on the SDO pin is available after the falling edge of

SCO and can be latched on the SCO rising edge. FSO goes low

at the beginning of a data transmission frame when the MSB is

available and returns high after 16 SCO cycles.

The frame sync input (FSI) can be used if the AD7722 conver-

sion process must be synchronized to an external source. FSI is

an optional signal; if FSI is grounded or tied high frame syncs

are internally generated. Frame sync allows the conversion data

presented to the serial interface to be a filtered and decimated

result derived from a known point in time. FSI can be applied

once after power-up, or it can be a periodic signal, synchronous to

CLKIN, occurring every 64 CLKIN cycles. When FSI is applied

for the first time, or if a low-to-high transition is detected that is not

synchronized to the output word rate, the next 127 conversions

should be considered invalid while the digital filter accumulates

new samples. Figure 4 shows how the frame sync signal resets

the serial output interface and how the AD7722 will begin to

output its serial data transmission frame. A common frame sync

signal can be applied to two or more AD7722s to synchronize

them to a common master clock.

2-Channel Multiplexed Operation

Three additional serial interface control pins (DOE, TSI, and

CFMT) are provided. The connection diagram in Figure 24

shows how they are used to allow the serial data outputs of two

AD7722s to easily share one serial data line. Since a serial data

transmission frame lasts 32 SCO cycles, two AD7722s can share

a single data line by alternating transmission of their 16-bit output

data onto one SDO pin.

CFMT

SDO

SFMT

SCO

TSI

FSO

FSI

DOE

CLKIN

AD7722

MASTER

FSI

DOE

CLKIN

SDO

CFMT

SCO

SFMT

FSO

TSI

AD7722

SLAVE

DGND

FROM

CONTROL

LOGIC

TO HOST

PROCESSOR

Figure 24. Connection for 2-Channel Multiplexed

Operation

The data output enable pin (DOE) controls SDO’s output buffer.

When the logic level on DOE matches the state of the TSI pin,

the SDO output buffer drives the serial dataline; otherwise, the

output of the buffer goes high impedance. The serial format pin

(SFMT) is set high to choose the frame sync output format. The

clock format pin (CFMT) is set high so that serial data is made

available on SDO after the rising edge of SCO and can be

latched on the SCO falling edge.

The master device is selected by setting TSI to a logic low and

connecting its FSO to DOE. The slave device is selected with its

TSI pin tied high, and both its FSI and DOE are controlled

from the master’s FSO. Since the FSO of the master controls

the DOE input of both the master and slave, one ADC’s SDO is

active while the other is high impedance (Figure 25). When the

master transmits its conversion result during the first 16 SCO

cycles of a data transmission frame, the low level on DOE sets

the slave’s SDO high impedance. Once the master completes

transmitting its conversion data, its FSO goes high and triggers

the slave’s FSI to begin its data transmission frame.

Following power up of the two devices, once the supplies have

settled, a synchronous RESET/SYNC pulse should be issued to

both ADCs to ensure synchronization. After a RESET/SYNC

has been issued, FSI can be applied to the master ADC to

allow continuous synchronization between the processor and

the ADCs. For continuous synchronization, FSI should not be

applied within four CLKIN cycles before an FSO (master) edge.

See Figure 25.

Serial Interfacing to DSPs

In serial mode, the AD7722 can be interfaced directly to several

industry-standard DSPs. In all cases, the AD7722 operates as

the master with the DSP operating as the slave. The AD7722

outputs its own serial clock (SCO) to transmit the digital word on

the SDO pin to a DSP. The DSP’s serial interface is synchronized

to the data transmission provided by the FSO signal.

Since the serial data clock from the AD7722 is always one-half

the CLKIN frequency, DSPs that can accept relatively high

serial clock frequencies are required. The ADSP-21xx family of

DSPs can operate with a maximum serial clock of 13.824 MHz;

the DSP56002 allows a maximum serial clock of 13.3 MHz; the

TMS320C5x-57 accepts a maximum serial clock of 10.989 MHz.