ADCMP565

Rev. 0 | Page 8 of 16

TIMING INFORMATION

50%

50%

50%

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

Q OUTPUT

LATCH ENABLE

02820-0-003

Figure 3. System Timing Diagram

The timing diagram in Figure 3 shows the ADCMP565 compare

and latch features. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol

Timing

Description

Input to output

high delay

Propagation delay measured from

the time the input signal crosses

the reference (± the input offset

voltage) to the 50% point of an

output low-to-high transition

Input to output

low delay

Propagation delay measured from

the time the input signal crosses

the reference (± the input offset

voltage) to the 50% point of an

output high-to-low transition

Latch enable

to output high

delay

Propagation delay measured from

the 50% point of the Latch Enable

signal low-to-high transition to

the 50% point of an output low-

to-high transition

Latch enable

to output low

delay

Propagation delay measured from

the 50% point of the Latch Enable

signal low-to-high transition to

the 50% point of an output high-

to-low transition

Symbol

Timing

Description

Minimum

hold time

Minimum time after the negative

transition of the Latch Enable

signal that the input signal must

remain unchanged to be acquired

and held at the outputs

Minimum

latch enable

pulse width

Minimum time that the Latch

Enable signal must be high to

acquire an input signal change

Minimum

setup time

Minimum time before the

negative transition of the Latch

Enable signal that an input signal

change must be present to be

acquired and held at the outputs

Output rise

time

Amount of time required to

transition from a low to a high

output as measured at the 20%

and 80% points

Output fall

time

Amount of time required to

transition from a high to a low

output as measured at the 20%

and 80% points

Voltage

overdrive

Difference between the

differential input and reference

input voltages