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DSPIC33FJ64GP706 数据表(PDF) 16 Page - Microchip Technology |
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DSPIC33FJ64GP706 数据表(HTML) 16 Page - Microchip Technology |
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16 / 322 page ![]() dsPIC33FJXXXGPX06/X08/X10 DS70286C-page 14 © 2009 Microchip Technology Inc. FIGURE 1-1: dsPIC33FJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM 16 OSC1/CLKI OSC2/CLKO VDD, VSS Timing Generation MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Precision Reference Band Gap FRC/LPRC Oscillators Regulator Voltage VCAP/VDDCORE UART1,2 ECAN1,2 DCI IC1-8 SPI1,2 I2C1,2 OC/ PORTA Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. PWM1-8 CN1-23 Instruction Decode and Control PCH PCL 16 Program Counter 16-bit ALU 23 23 24 23 Instruction Reg PCU 16 x 16 W Register Array ROM Latch 16 EA MUX 16 16 8 Interrupt Controller PSV and Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Address Latch Address Latch Program Memory Data Latch 16 16 16 16 Data Latch Address Latch 16 X RAM Y RAM 16 Y Data Bus X Data Bus DSP Engine Divide Support 16 DMA RAM DMA Controller Control Signals to Various Blocks ADC1,2 Timers PORTB PORTC PORTD PORTE PORTF PORTG Address Generator Units 1-9 |
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