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AS1122

Datasheet - D e t a i l e d D e s c r i p t i o n

PWM scheme of AS1122

The AS1122 uses a scrambled PWM scheme. Meaning the PWM value is divide into sup-periods (32 bits wide) and than evenly distributed over

the whole PWM cycle. If the PWM setting can not be divided by 32, the rest is added at the beginning of the PWM cycle.

Figure 39 shows some examples how different PWM settings are distributed over one PWM cycle.

Figure 39. Different PWM Outputs of AS1122

pulses (20 x 100ns) and stays then low for 4076 PWM-clock pulses (4076 x 100ns). After one PWM cycle (4096 pulses) the cycle is repeated

endless until the output channels is turned off or updated with new PWM data.