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PD720201 数据表(PDF) 21 Page - Renesas Technology Corp |
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PD720201 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 43 page ![]() μPD720201/μPD720202 3. ELECTRICAL SPECIFICATIONS R19DS0047EJ0500 Rev. 5.00 Page 21 of 40 Jan. 17, 2013 3.8.4 PCI Express CLKREQ# Table 3-13. PCI Express Interface – Power-Up and PECREQB Signal Timings Parameter Symbol Condition Min. Max. Units PONRSTB inactive to PECREQB Output active T PVCRL See Figure 3-10 1 μs Table 3-14. PCI Express Interface – PECREQB Clock Control Timings Parameter Symbol Condition Min. Max. Units PECREQB de-asserted high to clock parked T CRHOFF See Figure 3-11 0 ns PECREQB asserted low to clock active T CRLON See Figure 3-11 400 ns Figure 3-10. PCI Express Power-Up PECREQB Timing Figure 3-11. PCI Express PECREQB Clock Control Timing Power Stable VDD33 & VDD10 PONRSTB PECREQB PECLKP PECLKN PONRSTB inactive TPVCRL |
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