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AS3665 数据表(PDF) 8 Page - ams AG |
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AS3665 数据表(HTML) 8 Page - ams AG |
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8 / 78 page  www.austriamicrosystems.com Revision 1.0.2 7 - 77 AS3665 Datasheet, Confidential - Elect rical Chara c t e ri st ics Ti mi ng Diagra ms Timing Diagrams Figure 3. I 2C mode Timing Diagram 1. The logic input levels VIH and VIL allow for 1.8V supplied driving circuit 2. After this period the first clock pulse is generated. 3. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 4. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. 5. This feature can be disabled by setting auto_shutdown (see page 13)=0 SCL SDA tBUF tHD:STA tSU:STA REPEATED START tSU:STO tF tSU:DAT tHIGH tHD:DAT tR tLOW tHD:STA START STOP |
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