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AS3930 数据表(PDF) 21 Page - ams AG |
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AS3930 数据表(HTML) 21 Page - ams AG |
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21 / 32 page ![]() www.ams.com/LF-Receiver/AS3930 Revision 1.5 21 - 32 AS3930 Datasheet - Detailed Descr i p ti on If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not be longer than 40 bits (see bit rate definition in Table 19). The data pattern can be defined by the user and consists of two bytes which are stored in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first. The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern has to be repeated 2 times. Additionally, it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the Table 20. If the pattern is matched, then the wake-up interrupt is displayed on the WAKE output. If the pattern detection fails, then the internal wake-up is terminated with no signal sent to MCU and the false wake-up register will be incremented (R13<7:0>). The wake-up state is terminated with the direct command ‘clear_wake’ (see Table 12). This command terminates the MCU activity. The termination can also be automatic in case there is no response from MCU. The time out for automatic termination is set in a register R7<7:5>, as shown in the Table 21. 1 111 0 31 1056 528 1 111 1 32 1024 512 Table 20. Allowed Pattern Detection Errors R2<6> R2<5> Maximum allowed error in the pattern detection 0 0 No error allowed 0 1 1 missed zero 1 0 2 missed zeros 1 1 3 missed zeros Table 21. Timeout Setup R7<7> R7<6> R7<5> Timeout 00 0 0 sec 00 1 50 msec 01 0 100 msec 01 1 150 msec 10 0 200 msec 10 1 250 msec 11 0 300 msec 11 1 350 msec Table 19. Bit Rate Setup R7<4> R7<3> R7<2> R7<1> R7<0> Bit Duration in RTC Clock Periods Bit Rate (bits/s) Symbol Rate (Manchester symbols/s) |
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