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AS5045B

Datasheet - Application In form atio n

9.2 Alignment Mode

The alignment mode simplifies centering the magnet over the center of the chip to gain maximum accuracy.

Alignment mode can be enabled with the falling edge of CSn while PDIO = logic high (see Figure 13). The Data bits D11-D0 of the SSI change to

a 12-bit displacement amplitude output. A high value indicates large X or Y displacement, but also higher absolute magnetic field strength. The

magnet is properly aligned, when the difference between highest and lowest value over one full turn is at a minimum.

Under normal conditions, a properly aligned magnet will result in a reading of less than 128 over a full turn.

The MagINCn and MagDECn indicators will be = 1 when the alignment mode reading is < 128. At the same time, both hardware pins MagINCn

(#1) and MagDECn (#2) will be pulled to VSS. A properly aligned magnet will therefore produce a MagINCn = MagDECn = 1 signal throughout a

full 360º turn of the magnet.

Stronger magnets or short gaps between magnet and IC will show values larger than 128. These magnets are still properly aligned as long as

the difference between highest and lowest value over one full turn is at a minimum.

The Alignment mode can be reset to normal operation by a power-on-reset (disconnect / re-connect power supply) or by a falling edge on CSn

with PDIO = low.

Figure 13. Enabling the Alignment Mode

Figure 14. Exiting Alignment Mode

PDIO

CSn

AlignMode enable

Read-out

via SSI

2µs

min.

2µs

min.

PDIO

CSn

exit AlignMode

Read-out

via SSI