SLR2016, SLO2016, SLG2016, SLY2016, SCD5584A

2006-01-23

7

Block Diagram

IDBD5070

RAM Read Logic

D0

D1

D2

D3

D4

D6

D5

Memory

RAM

4 x 7 bit

Write

Address

Decoder

A0

WR

A1

Address

Bus

Row Decoder

ROM

ASCII

128 x 7 bit

Character

Decode

(4.48 kbits)

7-bit ASCII Code

Output

Column Data

Row Drivers

&

Row Control Logic

OSC

128

Counter

Counter

7

Rows 0 to 6

3

2

1

0

Timing and Control Logic

BL

Columns 0 to 19

Display

CLR

Logic

Display