CDC341

1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

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POST OFFICE BOX 655303

Clock-Distribution and Clock-Generation

Applications

Outputs

Switching Noise

Significantly Reduces Power Dissipation

Small-Outline (DW) Packages

description

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs

with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be

placed in a low state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for

customer use and should be strapped to GND.

The CDC341 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

1G

2G

A

1Y1 – 1Y4

2Y1 – 2Y4

X

X

L

L

L

L

LH

L

L

L

HH

L

H

H

LH

H

L

H

H

H

H

H

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙΒ is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1G

2G

A

P0

P1

2Y4

2Y3

GND

1Y1

1Y2

GND

1Y3

1Y4

GND

2Y1

2Y2

GND

DW PACKAGE

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