CDC7005

3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

SCAS685L− DECEMBER 2002 − REVISED JUNE 2009

19

POST OFFICE BOX 655303

application specific device characteristics over recommended operating free-air temperature

range (unless otherwise noted)

PARAMETER

REF_IN

PHASE

NOISE AT

VCXO

PHASE

NOISE AT

Yn PHASE NOISE AT

30.72 MHz

UNIT

PARAMETER

NOISE AT

30.72 MHz

NOISE AT

245.76 MHz

MIN

TYP†

MAX

UNIT

phn10

Phase noise at 10 Hz

−115

−77

−105

dBc/Hz

phn100

Phase noise at 100 Hz

−125

−95

−116

dBc/Hz

phn1k

Phase noise at 1 kHz

−131

−118

−135

dBc/Hz

phn10k

Phase noise at 10 kHz

−136

−136

−147

dBc/Hz

phn100k

Phase noise at 100 kHz

−138

−138

−152

dBc/Hz

phn240k

Phase noise at 240 kHz

−140

−143

−152

dBc/Hz

tstabi

PLL stabilization time, (see Note 15)

200

ms

† Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor.

NOTES: 15. The typical stabilization time is based on the above application example at a loop bandwidth of 20 Hz.

16. For further explanations as well as phase noise/jitter test results using various VCXOs, see application note SCAA067.