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AS8510 数据表(PDF) 39 Page - ams AG |
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AS8510 数据表(HTML) 39 Page - ams AG |
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39 / 47 page ![]() www.ams.com/AS8510 Revision 3.5 38 - 46 AS8510 Datasheet - Detailed Descr i p ti on 7.9.2 Initialization Sequence at Power ON Figure 16. AS8510 Device Initialization Sequence at Power ON Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > VPORHID. The duration period of Initialization is 500 μsec and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period. On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the first interrupt will occur after a time period of TADC. TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel registers and status registers are not read during the TDATA_INVALID duration. Example: Configuration registers are set as follows: CLK_REG = 8’b0010_0000 DEC_REG_R1_I = 0100_0101 DEC_REG_R2_I = 1100_0101 FIR_CTL_REG_I = 0000_0100 ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 16 are as follows: TDATA_STATUS_RD = 100 μsec (TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5) TDATA_INVALID = 8 μsec TADC = 1msec TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8 μsec CHOP_CLK and POR_N are internal signals of the device. Configure Device Start ADC DVDD/AVDD POR_N INT CHOP_CLK Channel Data Register 0x0000 DATA1 DATA2 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 500µS 1.5mS TDATA_STATUS_RD TDATA_VALID TDATA_INVALID VPORHID/VPORHIA TADC |
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