AT24C01

4

Note:

1. This parameter is characterized and is not 100% tested.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-

mally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL

high periods will indicate a start or stop condition as

defined below.

START CONDITION: A high-to-low transition of SDA with

SCL high is a start condition which must precede any other

command (refer to Start and Stop Definition timing dia-

gram).

STOP CONDITION: A low-to-high transition of SDA with

SCL high is a stop condition which terminates all communi-

cations. After a read sequence, the stop command will

place the EEPROM in a standby power mode (refer to Start

and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are seri-

ally transmitted to and from the EEPROM in 8-bit words.

Any device on the system bus receiving data (when com-

municating with the EEPROM) must pull the SDA bus low

to acknowledge that it has successfully received each

word. This must happen during the ninth clock cycle after

each word received and after all other system devices have

freed the SDA bus. The EEPROM will likewise acknowl-

edge by pulling SDA low after receiving each address or

data word (refer to Acknowledge Response from Receiver

timing diagram).

STANDBY MODE: The AT24C01 features a low power

standby mode which is enabled: (a) upon power-up and (b)

after the receipt of the STOP bit and the completion of any

internal operations.

MEMORY RESET: After an interruption in protocol, power

loss or system reset, any 2-wire part can be reset by follow-

ing these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle

while SCL is high and then (c) create a start condition as

SDA is high.

AC Characteristics

Applicable over recommended operating range from T

100 pF (unless otherwise noted).

Symbol

Parameter

2.7-, 2.5-, 1.8-volt

5.0-volt

Units

Min

Max

Min

Max

f

SCL

Clock Frequency, SCL

100

400

KHz

t

LOW

Clock Pulse Width Low

4.7

1.2

µs

t

HIGH

Clock Pulse Width High

4.0

0.6

µs

t

I

100

50

ns

t

AA

Clock Low to Data Out Valid

0.1

4.5

0.1

0.9

µs

t

BUF

Time the bus must be free before a new

4.7

1.2

µs

t

HD.STA

Start Hold Time

4.0

0.6

µs

t

SU.STA

Start Set-up Time

4.7

0.6

µs

t

HD.DAT

Data In Hold Time

0

0

µs

t

SU.DAT

Data In Set-up Time

200

100

ns

t

R

1.0

0.3

µs

t

F

300

300

ns

t

SU.STO

Stop Set-up Time

4.7

0.6

µs

t

DH

Data Out Hold Time

100

50

ns

t

WR

Write Cycle Time

10

10

ms

5.0V, 25°C, Page Mode

1M

1M

Write

Cycles