3

AT45DB321B

2223D–DFLASH–10/02

Memory Architecture Diagram

Device Operation

The device operation is controlled by instructions from the host processor. The list of

instructions and their associated opcodes are contained in Tables 1 through 4. A valid

instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode

and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK pin controls the loading of the opcode and the desired buffer or main

memory address location through the SI (serial input) pin. All instructions, addresses

and data are transferred with the most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to

denote the ten address bits required to designate a byte address within a buffer. Main

memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0

where PA12 - PA0 denotes the 13 address bits required to designate a page address

and BA9 - BA0 denotes the ten address bits required to designate a byte address within

the page.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from

either one of the two data buffers. The DataFlash supports two categories of read

modes in relation to the SCK signal. The differences between the modes are in respect

to the inactive state of the SCK signal as well as which clock cycle data will begin to be

output. The two categories, which are comprised of four modes total, are defined as

Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI

Mode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used to

select which category will be used for reading. Please refer to the “Detailed Bit-level

Read Timing” diagrams in this datasheet for details on the clock cycle sequences for

each mode.

CONTINUOUS ARRAY READ: By supplying an initial starting address for the main

memory array, the Continuous Array Read command can be utilized to sequentially

read a continuous stream of data from the device by simply providing a clock signal; no

additional addressing information or control signals need to be provided. The DataFlash

incorporates an internal address counter that will automatically increment on every clock

SECTOR 0 = 4224 bytes (4K + 128)

SECTOR 1 = 266,112 bytes (252K + 8064)

SECTOR 15 = 270,336 bytes (256K + 8K)

Block = 4224 bytes

(4K + 128)

8 Pages

SECTOR 0

Page = 528 bytes

(512 + 16)

PAGE 0

PAGE 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 8190

PAGE 8191

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

PAGE 8189

SECTOR ARCHITECTURE

BLOCK ARCHITECTURE

PAGE ARCHITECTURE

BLOCK 0

BLOCK 1

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

BLOCK 1022

BLOCK 1023

BLOCK 126

BLOCK 127

BLOCK 128

BLOCK 129

SECTOR 2 = 270,336 bytes (256K + 8K)

SECTOR 16 = 270,336 bytes (256K + 8K)

BLOCK 2