DAC8412/DAC8413

Data Sheet

Rev. G | Page 14 of 20

THEORY OF OPERATION

INTRODUCTION

The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel

input DACs featuring a 12-bit data bus with readback capability.

The only differences between the DAC8412/DAC8413 are the

reset functions. The DAC8412 resets to midscale (Code 0x800),

and the DAC8413 resets to minimum scale (Code 0x000).

The ability to operate from a single 5 V supply is a unique

feature of these DACs.

Operation of the DAC8412/DAC8413 can be viewed by

dividing the system into three separate functional groups: the

digital I/O and logic, the digital-to-analog converters, and the

output amplifiers.

DACS

Each DAC is a voltage switched, high impedance (R = 50 kΩ),

R-2R ladder configuration. Each 2R resistor is driven by a pair

GLITCH

Worst-case glitch occurs at the transition between Half-Scale

Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111

1111 1111. It can be measured at about 2 V μs (see Figure 36).

For demanding applications such as waveform generation or

precision instrumentation control, a deglitcher circuit can be

implemented with a standard sample-and-hold circuit (see

Figure 37). When CS is enabled by synchronizing the hold

period to be longer than the glitch tradition, the output voltage

can be smoothed with minimum disturbance. A quad

sample-and-hold amplifier, SMP04, has been used to illustrate

the deglitching result (see Figure 36).

S/H

CS

DACOUT

DACOUT

S/H

HS

H

S

Figure 37. Data Output (Read Timing)

REFERENCE INPUTS

the output high and low voltage limits of all four of the DACs.

Each reference input has voltage restrictions with respect to the

because of these restrictions, the DAC8412 references cannot be

current-sinking capability and must be buffered with an

requirements.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with ±10 V references. This

limits the reference bandwidth.

DIGITAL I/O

See Table 6 for the digital control logic truth table. Digital I/O

consists of a 12-bit bidirectional data bus, two registers select

inputs, A0 and A1, a R/W input, a RESET input, a chip select (CS),

and a load DAC (LDAC) input. Control of the DACs and bus

direction is determined by these inputs as shown in Table 6. Digital

data bits are labeled with the MSB defined as Data Bit 11 and the

LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.

See Figure 38 for a simplified I/O logic diagram. The register

select inputs A0 and A1 select individual DAC registers A

(Binary Code 00) through D (Binary Code 11). Decoding of the

registers is enabled by the CS input. When CS is high, no

decoding takes place, and neither the writing nor the reading of

the input registers is enabled. The loading of the second bank of

registers is controlled by the asynchronous LDAC input. By

taking LDAC low while CS is enabled, all output registers can

width for updating all DACs is a minimum of 170 ns.

The R/W input, when enabled by CS, controls the writing to

and reading from the input register.

CODING

Both DAC8412/DAC8413 use binary coding. The output

voltage can be calculated by

4096

)

(

N

V

V

V

V

REFL

REFH

REFL

OUT









where N is the digital code in decimal.