I2CSTAT datasheet(128/210 Pages) MICROCHIP

128 / 210 page

dsPIC30F2011/2012/3012/3013

DS70139G-page 128

17.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM Configuration bits (clock

switch and monitor selection bits) in the FOSC Device

Configuration register. If the FSCM function is enabled,

the LPRC internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control by

the SWDTEN bit.

In the event of an oscillator failure, the FSCM will gen-

erate a clock failure trap event and will switch the sys-

tem clock over to the FRC oscillator. The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) bit (OSCCON<3>) is also set

whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If the oscillator has a very slow start-up time coming out

of POR, BOR or Sleep, it is possible that the PWRT

timer will expire before the oscillator has started. In

such cases, the FSCM will be activated and the FSCM

will initiate a clock failure trap, and the COSC<2:0> bits

are loaded with FRC oscillator selection. This will

effectively shut-off the original oscillator that was trying

to start.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC oscillator as follows:

The COSC bits (OSCCON<14:12>) are loaded

with the FRC oscillator selection value.

CF bit is set (OSCCON<3>).

OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

• Primary (with or without PLL)

• Secondary

• Internal FRC

• Internal LPRC

The user can switch between these functional groups

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group

always

determined

the

FPR<4:0>

Configuration bits.

The OSCCON register holds the Control and Status

bits related to clock switching.

• COSC<2:0>: Read-only bits always reflect the

current oscillator group in effect.

• NOSC<2:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<2:0> and

NOSC<2:0> are both loaded with the

Configuration bit values FOS<2:0>.

• LOCK: The LOCK bit indicates a PLL lock.

• CF: Read-only bit indicating if a clock fail detect

has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If Configuration bits FCKSM<1:0> = 1x, then the clock

switching and Fail-Safe Clock monitoring functions are

disabled. This is the default Configuration bit setting.

If clock switching is disabled, then the FOS<2:0> and

FPR<4:0> bits directly control the oscillator selection

and the COSC<2:0> bits do not control the clock selec-

tion. However, these bits will reflect the clock source

selection.

17.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

Byte Write 0x46 to OSCCON low

Byte Write 0x57 to OSCCON low

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte Write 0x78 to OSCCON high

Byte Write 0x9A to OSCCON high

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 kHz when the Fail-Safe Clock Monitor

is enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast

RC oscillator.

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