LTC2859/LTC2861

12

285961fb

The resistance is maintained over the entire RS485 common

mode range of –7V to +12V as shown in Figure 11.

The integrated termination resistor has a high frequency

response which does not limit performance at the maximum

specified data rate. Figure 12 shows the magnitude and

phase of the termination impedance vs frequency.

Supply Current

The unloaded static supply currents in the LTC2859/

LTC2861 are very low —typically under 700μA for all modes

of operation without the internal terminator enabled. In

applications with resistively terminated cables, the supply

current is dominated by the driver load. For example, when

using two 120Ω terminators with a differential driver output

voltage of 2V, the DC current is 33mA, which is sourced

by the positive voltage supply. This is true whether the

terminators are external or internal such as in the LTC2859/

LTC2861. Power supply current increases with toggling

data due to capacitive loading and this term can increase

significantly at high data rates. Figure 13 shows supply

current vs data rate for two different capacitive loads (for

the circuit configuration of Figure 3).

High Speed Considerations

A ground plane layout is recommended for the LTC2859/

LTC2861. A 0.1μF bypass capacitor less than one quarter

board traces connected to signals A/B and Z/Y (LTC2861)

should be symmetrical and as short as possible to maintain

good differential signal integrity. To minimize capacitive

effects, the differential signals should be separated by more

than the width of a trace and should not be routed on top

of each other if they are on different signal planes.

Care should be taken to route outputs away from any

sensitive inputs to reduce feedback effects that might

cause noise, jitter, or even oscillations. For example, in

the full duplex LTC2861, DI and A/B should not be routed

near the driver or receiver outputs.

The logic inputs of the LTC2859/LTC2861 have 50mV of

hysteresis to provide noise immunity. Fast edges on the

outputs can cause glitches in the ground and power supplies

which are exacerbated by capacitive loading. If a logic input

is held near its threshold (typically 1.5V), a noise glitch

Figure 11. Termination Resistance

vs Common Mode Voltage

Figure 12. Termination Magnitude

and Phase vs Frequency

Figure 13. Supply Current vs Data Rate

APPLICATIONS INFORMATION

COMMON MODE VOLTAGE (V)

–10

130

140

10

285961 F11

120

110

–5

0

5

15

150

FREQUENCY (MHz)

0

20

40

60

80

100

120

140

285961 F12

–25

–20

–15

–10

–5

0

MAGNITUDE

PHASE

DATA RATE (kbps)

45

50

55

60

65

70

75

285961 F13