FG256 datasheet(2/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

I/Os Per Package 1

ProASIC3L

Low-Power

Devices

A3P250L 2

A3P600L

A3P1000L

A3PE3000L

ARM

Cortex-M1

Devices

M1A3P600L

M1A3P1000L

M1A3PE3000L 3

Package

I/O Type

Single-

Ended I/O 4

Differential

I/O Pairs

Single-

Ended I/O 4

Differential

I/O Pairs

Single-

Ended I/O 4

Differential

I/O Pairs

Single-

Ended I/O 4

Differential

I/O Pairs

VQ100

–

––

PQ208

151

154

147

FG144

2497259725

FG256

157

177

–

FG324

–

221

110

FG484

–

235

300

341

168

FG896

–

620

310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure

you are complying with design and board migration requirements.

2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.

3. ARM Cortex-M1 support is TBD on this device.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. FG256 and FG484 are footprint-compatible packages.

6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the part

number.

7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user

I/Os available is reduced by one.

Table 2 • ProASIC3L FPGAs Package Sizes Dimensions

Package

VQ100

PQ208

FG144

FG256

FG324

FG484

FG896

Length × Width

(mm\mm)

14 × 14

28 × 28

13 × 13

17 × 17

19 × 19

23 × 23

31 × 31

Nominal Area

(mm2)

196

784

169

289

361

529

961

Pitch (mm)

0.5

1.0

Height (mm)

1.00

3.40

1.45

1.60

1.63

2.23

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