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74LVC00APW 数据表(PDF) 6 Page - NXP Semiconductors |
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74LVC00APW 数据表(HTML) 6 Page - NXP Semiconductors |
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6 / 14 page ![]() 74LVC00A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 25 April 2012 6 of 14 NXP Semiconductors 74LVC00A Quad 2-input NAND gate Test data is given in Table 8. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator Fig 7. Load circuitry for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Table 8. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC ≤ 2 ns 30 pF 1 k Ω 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 k Ω 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω 2.7V 2.7V ≤ 2.5 ns 50 pF 500 Ω 3.0Vto 3.6V 2.7V ≤ 2.5 ns 50 pF 500 Ω |
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