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7

ISO150

LOGIC LEVELS

A single pin serves as a data input or output, depending on

the mode selected. Logic inputs are CMOS with thresholds

set for TTL compatibility. The logic threshold is approxi-

mately 1.3V with 5V supplies and with approximately 400mV

of hysteresis. Input logic thresholds vary with the power

supply voltage. Drive the logic inputs with signals that swing

the full logic voltage swing. The ISO150 will use somewhat

greater quiescent current if logic inputs do not swing within

0.5V of the power supply rails.

In receive mode, the data output can drive 15 standard

LS-TTL loads. It will also drive CMOS loads. The output

drive circuits are CMOS.

POWER SUPPLY

Separate, isolated power supplies must be connected to side

A and side B to provide galvanic isolation. Nominal rated

supply voltage is 5V. Operation extends from 3V to 5.5V.

Power supplies should be bypassed close to the device pins

on both sides of the isolation barrier.

channel 1 and 2. The specified supply current is the total of

both transceivers on one side, both operating in the indicated

mode. Supply current for one transceiver in transmit mode

and one in receive mode can be estimated by averaging the

specifications for transmit and receive operation. Supply

current varies with the data transmission rate—see typical

curves.

POWER-UP STATE

The ISO150 transmits information across the barrier only

when the input-side data changes logic state. When a trans-

ceiver is first programmed for receive mode, or is powered-

up in receive mode, its output is initialized “high”. Subse-

quent changes of data applied to the input side will cause the

output to properly reflect the input side data.

SIGNAL LOSS

The ISO150’s differential-mode signal transmission and

careful receiver design make it highly immune to voltage

across the isolation barrier (isolation-mode voltage). Rapidly

changing isolation-mode voltage can cause data errors. As

the rate of change of isolation voltage is increased, there is

a very sudden increase in data errors. Approximately 50% of

ISO150s will begin to produce data errors with isolation-

mode transients of 1.6kV/

µs. This may occur as low as

500V/

µs in some devices. In comparison, a 1000Vrms, 60Hz

isolation-mode voltage has a rate of change of approximately

0.5V/

µs.

Still, some applications with large, noisy isolation-mode

voltage can produce data errors by causing the receiver

output to change states. After a data error, subsequent changes

in input data will produce correct output data.

PROPAGATION DELAY AND SKEW

Logic transitions are delayed approximately 27ns through

the ISO150. Some applications are sensitive to data skew—

the difference in propagation delay between channel 1 and

channel 2. Skew is less than 2ns between channel 1 and

channel 2. Applications using more than one ISO150 must

allow for somewhat greater skew from device to device.

Since all devices are tested for delay times of 20ns min to

40ns max, 20ns is the largest device-to-device data skew.

MODE CHANGES

The transmission direction of a channel can be changed “on

the fly” by reversing the logic levels at the channel’s R/T

pins on both side A and side B. Approximately 75ns after the

transceiver is programmed to receive mode its output is

initialized “high”, and will respond to subsequent input-side

changes in data.

STANDBY MODE

Quiescent current of each transceiver circuit is very low in

transmit mode when input data is not changing (1nA typi-

cal). To conserve power when data transmission is not

required, program both side A and B transceivers for trans-

mit mode. Input data applied to either transceiver is ignored

by the other side. High speed data applied to either trans-

ceiver will increase quiescent current.

CIRCUIT LAYOUT

The high speed of the ISO150 and its isolation barrier

require careful circuit layout. Use good high speed logic

layout techniques for the input and output data lines. Power

supplies should be bypassed close to the device pins on both

sides of the isolation barrier. Use low inductance connec-

tions. Ground planes are recommended.

Maintain spacing between side 1 and side 2 circuitry equal

or greater than the spacing between the missing pins of the

ISO150 (approximately 16mm for the DIP version). Sockets

are not recommended.