5-327

FAST AND LS TTL DATA

QUAD D FLIP-FLOP

The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The

device is useful for general flip-flop requirements where clock and clear inputs

are common. The information on the D inputs is stored during the LOW to

HIGH clock transition. Both true and complemented outputs of each flip-flop

are provided. A Master Reset input resets all flip-flops, independent of the

Clock or D inputs, when LOW.

The LS175 is fabricated with the Schottky barrier diode process for high

speed and is completely compatible with all Motorola TTL families.

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

MR

Q3

Q3

D3

D2

Q2

Q2

CP

Q0

Q0

D0

D1

Q1

Q1 GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

D0 – D3

CP

MR

Q0 – Q3

Q0 – Q3

Data Inputs

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

True Outputs (Note b)

Complemented Outputs (Note b)

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 (2.5) U.L.

5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

LOGIC DIAGRAM

D Q

CP

CD

Q

CP D3

D2

D1

D0

Q3

Q3

Q2

Q2

Q1

Q1

Q0

Q0

D Q

CP

CD

Q

MR

14

1

2

6

7

3

4

5

9

11

12

10

13

15

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

D Q

CP

CD

Q

D Q

CP

CD

Q

SN54/74LS175

QUAD D FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

12

1

2

3

6

7 11

14 15

10

4

5

13

9

CP

D0

D1

D2

D3

MR

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3