5-436

FAST AND LS TTL DATA

SN54/74LS259

ts

Figure 1. Turn-on and Turn-off Delays, Enable To

Output and Enable Pulse Width

Figure 4. Setup and Hold Time, Data to Enable

Figure 2. Turn-on and Turn-off Delays,

Data to Output

Figure 3. Turn-on and Turn-off Delays,

Address to Output

Figure 5. Turn-on Delay, Clear to Output

Figure 6. Setup Time, Address to Enable

(See Notes 1 and 2)

NOTES:

1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is

addressed and the other latches are not affected.

2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.

OTHER CONDITIONS: C = H, A = STABLE

OTHER CONDITIONS: E = L, C = H, A = STABLE

OTHER CONDITIONS: E = L, C = L, D = H

OTHER CONDITIONS: C = H, A = STABLE

OTHER CONDITIONS: E = H

1.3 V

tPHL

tPLH

1.3 V

D

E

Q

1.3 V

1.3 V

1.3 V

1.3 V

tPLH

tPHL

D

Q

1.3 V

1.3 V

tPHL

C

Q

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

A1

A1

Q1

tPLH

D

E

Q

th(H)

th(L)

1.3 V

OTHER CONDITIONS: C = H

STABLE ADDRESS

A

E

ts(H)

ts(L)

tPHL

tw

tw

Q=D

Q=D

AC WAVEFORMS