5-4

FAST AND LS TTL DATA

SN54/74LS322A

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

35

MHz

CL = 15 pF

tPHL

tPLH

Propagation Delay, Clock

to QH′

26

22

35

33

ns

CL = 15 pF

tPHL

Propagation Delay, Clear

to QH′

27

35

ns

L = 15 pF

tPHL

tPLH

Propagation Delay, Clock

to QA– QH

22

16

33

25

ns

CL = 45 pF,

RL = 667 Ω

tPHL

Propagation Delay, Clear

to QA– QH

22

35

ns

CL = 45 pF,

RL = 667 Ω

tPZH

tPZL

Output Enable Time

15

15

35

35

ns

tPHZ

tPLZ

Output Disable Time

15

15

25

25

ns

CL = 5.0 pF

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

Clock Pulse Width HIGH

25

ns

VCC = 5.0 V

tW

Clock Pulse Width LOW

15

ns

VCC = 5.0 V

tW

Clear Pulse Width LOW

20

ns

VCC = 5.0 V

ts

Data Setup Time

20

ns

VCC = 5.0 V

ts

Select Setup Time

15

ns

VCC = 5.0 V

th

Data Hold Time

0

ns

th

Select Hold Time

10

ns

trec

Recovery Time

20

ns

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time required

for the correct logic level to be present at the logic input prior to

the clock transition from LOW-to-HIGH in order to be recog-

nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

the clock transition from LOW-to-HIGH that the logic level

must be maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the correct

logic level may be released prior to the clock transition from

LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH Data to the Q outputs.