5-2

FAST AND LS TTL DATA

SN54/74LS323

LOGIC DIAGRAM

S1

S0

DS0

SR

Q0

OE1

OE2

D

Q

CP

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DS7

Q7

14

1

2

6

7

3

8

4

5

9

11

12

13

15

16

17

18

19

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

CP

FUNCTIONAL DESCRIPTION

The logic diagram and truth table indicate the functional

characteristics of the SN54/74LS323 Universal Shift/Storage

Register. This device is similar in operation to the

SN54/74LS299 except for synchronous reset. A partial list of

the common features are described below:

1. They use eight D-type edge-triggered flip-flops that re-

spond only to the LOW-to-HIGH transition of the Clock

(CP). The only timing restriction, therefore, is that the mode

control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may

be stable at least a setup time prior to the positive transition

of the Clock Pulse.

2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops

Q0–Q7 respectively, and the outputs of Q0–Q7 are in the

high impedance state regardless of the state of OE1 or

OE2.

An important unique feature of the SN54/74LS323 is a fully

Synchronous Reset that requires only to be stable at least one

setup time prior to the positive transition of the Clock Pulse.

TRUTH TABLE

INPUTS

RESPONSE

SR

S1

S0

OE1 OE2

CP

DS0 DS7

L

X

X

H

X

X

X

Synchronous Reset; Q0 = Q7 = LOW

I/O voltage undetermined

L

X

X

X

H

X

X

Synchronous Reset; Q0 = Q7 = LOW

I/O voltage undetermined

L

H

H

X

X

X

X

I/O voltage undetermined

L

L

X

L

L

X

X

Synchronous Reset; Q0 = Q7 = LOW

L

X

L

L

L

X

X

I/O voltage LOW

H

L

H

X

X

D

X

Shift Right; D

Q0; Q0 Q1; etc.

H

L

H

L

L

D

X

Shift Right; D

Q0 & I/O0; Q0 Q1 & I/O1; etc.

H

H

L

X

X

X

D

Shift Left; D

Q7; Q7 Q6; etc.

H

H

L

L

L

X

D

Shift Left; D

Q7 & I/O7; Q7 Q6 & I/O6; etc.

H

H

H

X

X

X

X

Parallel Load I/On Qn

H

L

L

H

X

X

X

X

Hold; I/O Voltage Undetermined

H

L

L

X

H

X

X

X

Hold; I/O Voltage Undetermined

H

L

L

L

L

X

X

X

Hold; I/On = Qn

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial