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DPAD2 数据表(PDF) 2 Page - Calogic, LLC

部件名 DPAD2
功能描述  Dual Pico Amp Diodes
PDF  2 Pages
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制造商  CALOGIC [Calogic, LLC]
网页  http://www.calogic.net
标志 CALOGIC - Calogic, LLC

DPAD2 数据表(HTML) 2 Page - Calogic, LLC

  DPAD2 Datasheet HTML 1Page - Calogic, LLC DPAD2 Datasheet HTML 2Page - Calogic, LLC  
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DPAD1 / DPAD2 / DPAD5 / DPAD10 / DPAD20 / DPAD50 / DPAD100
SSTDPAD5 / SSTDPAD10 / SSTDPAD20 / SSTDPAD50 / SSTDPAD100
CORPORATION
ABSOLUTE MAXIMUM RATINGS (25
oC)
Forward Gate Current, Each Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Total Device Dissipation @ TA = 25
oC
Derate 4.0 mW/
oC to 125oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125
oC
Lead Temperature (1/16" from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
oC
ELECTRICAL CHARACTERISTICS (25
oC unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
TEST CONDITIONS
STATIC
IR
Reverse Current
-1
pA
VR = -20 V
DPAD1
-2
DPAD2
-5
DPAD5
-10
DPAD10
-20
DPAD20
-50
DPAD50
-100
DPAD100
BVR
Breakdown Voltage (Reverse)
-45
-120
V
IR = -1
µA
DPAD1, 2, 5
-35
DPAD10, 20, 50, 100
VF
Forward Voltage Drop
0.8
1.5
IF = 5 mA
DPAD1, 2, 5, 10, 20, 50, 100
DYNAMIC
CR
Capacitance
0.8
pF
VR = -5 V, f = 1 MHz
DPAD1, 2, 5
2.0
DPAD10, 20, 50, 100
| CR1 - CR2 |
Differential Capacitance
0.1
0.2
pF
VR1 = VR2 = -5 V, f = 1 MHz
DPAD1, 2, 5, 10, 20, 50, 100
APPLICATION
Operational Amplifier Protection. Input Differential Voltage
limited to 0.8 V (typ) by DPADS D1 and D2 Common mode
input voltage limited by DPADS D3 and D4 to
±15V.
Typical sample and hold circuit with clipping, DPAD diodes
reduce offset voltages fed capacitively from the FET switch
gate.
DPAD10
D1
D4
+
1
-15V
+15V
_
D2
D3
I < 1 pA
R
+V
-V
DPAD1
VOUT
C
CONTROL SIGNAL
ein
+
DPAD1
J110
J210



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