5-533

FAST AND LS TTL DATA

OCTAL D FLIP-FLOP WITH ENABLE;

HEX D FLIP-FLOP WITH ENABLE;

4-BIT D FLIP-FLOP WITH ENABLE

The SN54 / 74LS377 is an 8-bit register built using advanced Low Power

Schottky technology. This register consists of eight D-type flip-flops with a

buffered common clock and a buffered common clock enable.

The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable.

This device is similar to the SN54 / 74LS174, but with common Enable rather

than common Master Reset.

The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This

device is similar to the SN54 / 74LS175 but features the common Enable

rather then common Master Reset.

PIN NAMES

LOADING (Note a)

HIGH

LOW

E

Enable (Active LOW) Input

0.5 U.L.

0.25 U.L.

D0 – D3

Data Inputs

0.5 U.L.

0.25 U.L.

CP

Clock (Active HIGH Going Edge) Input

0.5 U.L.

0.25 U.L.

Q0 – Q3

True Outputs (Note b)

10 U.L.

5 (2.5) U.L.

Q0 – Q3

Complemented Outputs (Note b)

10 U.L.

5 (2.5) U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) Temperature Ranges.

SN54/74LS377

SN54/74LS378

SN54/74LS379

OCTAL D FLIP-FLOP WITH

ENABLE; HEX D FLIP-FLOP

WITH ENABLE; 4-BIT D FLIP-FLOP

WITH ENABLE

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXDW SOIC

SN74LSXXXD

SOIC

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

16

1

D SUFFIX

SOIC

CASE 751B-03

20

1

J SUFFIX

CERAMIC

CASE 732-03

20

1

N SUFFIX

PLASTIC

CASE 738-03

20

1

DW SUFFIX

SOIC

CASE 751D-03