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AD5686 数据表(PDF) 7 Page - Analog Devices

部件名 AD5686
功能描述  Quad, 16-/12-Bit nanoDAC with SPI Interface
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5686 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
AD5686/AD5684
Rev. A | Page 7 of 28
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol
Min
Max
Min
Max
Unit
SCLK Cycle Time
t1
66
40
ns
SCLK High Time
t2
33
20
ns
SCLK Low Time
t3
33
20
ns
SYNC to SCLK Falling Edge
t4
33
20
ns
Data Setup Time
t5
5
5
ns
Data Hold Time
t6
5
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
15
10
ns
Minimum SYNC High Time
t8
60
30
ns
Minimum SYNC High Time
t9
60
30
ns
SDO Data Valid from SCLK Rising Edge
t10
36
25
ns
SCLK Falling Edge to SYNC Rising Edge
t11
15
10
ns
SYNC Rising Edge to SCLK Rising Edge
t12
15
10
ns
1
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy-Chain Timing Diagram
200µA
IOL
200µA
IOH
VOH (MIN)
TO OUTPUT
PIN
CL
20pF
t4
t5
t6
t8
SDO
SDIN
SYNC
SCLK
48
24
DB23
DB0
DB23
DB0
DB23
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
DB0
t11
t12
t10



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