www.austriamicrosystems.com

Revision 1.02

21 - 51

AS3400 AS3410 AS3430 1v0

Data Sheet - D e t a i l e d D e s c r i p t i o n

8.5.4 Status Indication

AS3410and AS3430 features a on-status information via the current output pin ILED. The current can be controlled in 3 steps and be switched

off, by setting the PWM to 0%, 25%, 50% or 100% duty cycle of a 50kHz signal.

If LOW_BAT is active, ILED switches to blinking with 1Hz, 50% duty cycle and 50% current setting.

8.6 VNEG Charge Pump

The VNEG charge pump uses one external 1uF capacitor to generate a negative supply voltage out of the battery input voltage to supply all

audio related blocks. This allows a true-ground headphone output with no more need of external dc-decoupling capacitors.

8.6.1 Parameter

8.7 OTP Memory & Internal Registers

The OTP memory consists of OTP register and the OTP fuses.The OTP register can be written as often as wanted but will lose the content on

power off. The OTP fuses are intended to store basic chip configurations as well as the microphone gain settings to optimize the ANC

performance and get rid of sensitivity variations of different microphones. Burning the fuses can only be done once and is a permanent change,

which means the fuses keep the content even if the chip is powered down. This AS3400/10/30 offers 4 register set for storing the microphone

gain making it possible to change the gain 3 times for re-calibration or other purposes.

When the chip is controlled by a microcontroller via I2C, the OTP memory don’t has to be used.

8.7.1 Register & OTP Memory Configuration

Figure 19 is showing the principal register interaction.

Figure 19. Register Access

Table 11. Headphone Output Parameter

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input voltage

VBAT

1.0

1.5

1.8

V

Output voltage

VNEG

-0.7

-1.5

-1.8

V

External flying capacitor

1µF

OTP Register

10h...16h; 30h...35h

OTP

Fuses

BURN

LOAD

Register

0x8,0x9,0xA

0xB, 0xC, 0x21

OTP WRITE

OTP READ

normal I2C write

normal I2C read

Register

8h...21h

OTP path is default

but can be switched

by register setting