9

CAT25C01/02/04/08/16

Doc. No. 25067-00 5/00

Advanced Information

Figure 9.

HOLD

HOLD

HOLD

HOLD

HOLD Timing

DESIGN CONSIDERATIONS

The CAT25C01/02/04/08/16

powers up in a write

disable state and in a low power standby mode. A

WREN instruction must be issued to perform any writes

to the device after power up. Also,on power up

CS

should be brought low to enter a ready state and

receive an instruction. After a successful byte/page

write or status register write, the CAT25C01/02/04/08/

16 goes into a write disable mode.

CS must be set high

Figure 8. Page Write Instruction Timing

Note: Dashed Line= mode (1, 1) – ––––

Note: Dashed Line= mode (1, 1) – ––––

SK

SI

SO

0

0

0

0

0

0

1

0

ADDRESS

Data

Byte 1

012345678

21

22

23 24-31

32-39

Data

Byte 2

Data

Byte 3

Data Byte N

CS

OPCODE

7..1

0

24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

DATA IN

HIGH IMPEDANCE

CS

SCK

HOLD

SO

tCD

tHD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

Figure 10.

WP

WP

WP

WP

WP Timing

Note: Dashed Line= mode (1, 1) – ––––

CS

SCK

WP

WP

after the proper number of clock cycles to start an

internal write cycle. Access to the array during an

internal write cycle is ignored and programming is

continued. On power up, SO is in a high impedance. If

an invalid op code is received, no data will be shifted

into the CAT25C01/02/04/08/16, and the serial output

pin (SO) will remain in a high impedance state until the

falling edge of

CS is detected again.