ADP2138/ADP2139

Data Sheet

Rev. C | Page 14 of 20

6

5

4

3

2

1

0

0

1

2

3

4

5

6

DC BIAS VOLTAGE (V)

Figure 35. Typical Capacitor Performance

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

(

)

OUT

SW

IN

RIPPLE

C

L

f

V

V

×

×

×

×

=

2

2π

OUT

SW

RIPPLE

C

f

I

×

×

=

8

Capacitors with lower equivalent series resistance (ESR) are

preferred to guarantee low output voltage ripple, as shown in

the following equation:

RIPPLE

RIPPLE

COUT

I

V

ESR

≤

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is 3 µF.

Table 7. Suggested 4.7 μF Capacitors

Vendor

Type

Model

Case

Size

Voltage

Rating (V)

Murata

X5R

GRM188R60J475

0603

6.3

Taiyo Yuden

X5R

JMK107BJ475

0603

6.3

Coilcraft

TDK

X5R

C1608X5R0J475

0603

6.3

Input Capacitor

Higher value input capacitors help to reduce the input voltage

ripple and improve transient response. Maximum input

capacitor current is calculated using the following equation:

IN

OUT

IN

OUT

MAX

LOAD

CIN

V

V

V

V

I

I

)

(

)

(

−

≥

To minimize supply noise, place the input capacitor as close to

the VIN pin of the ADP2138/ADP2139 as possible. As with the

output capacitor, a low ESR capacitor is recommended. The list

of recommended capacitors is shown in Table 8.

Table 8. Suggested 4.7 μF Capacitors

Vendor

Type

Model

Case

Size

Voltage

Rating (V)

Murata

X5R

GRM188R60J475

0603

6.3

Taiyo Yuden

X5R

JMK107BJ475

0603

6.3

Coilcraft

TDK

X5R

C1608X5R0J475

0603

6.3

THERMAL CONSIDERATIONS

Because of the high efficiency of the ADP2138/ADP2139, only a

small amount of power is dissipated inside the ADP2138/ADP2139

package, which reduces thermal constraints.

However, in applications with maximum loads at high ambient

temperature, low supply voltage, and high duty cycle, the heat

dissipated in the package is great enough that it may cause the

junction temperature of the die to exceed the maximum junc-

tion temperature of 125°C. If the junction temperature exceeds

150°C, the converter enters thermal shutdown. It recovers when

the junction temperature falls below 130°C.

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to power dissipation, as shown in the following

equation:

where:

dissipation.

The rise in temperature of the package is directly proportional

to the power dissipation in the package. The proportionality

constant for this relationship is the thermal resistance from the

junction of the die to the ambient temperature, as shown in the

following equation:

where:

ambient temperature of the package.

PCB LAYOUT GUIDELINES

Poor layout can affect ADP2138/ADP2139 performance, causing

EMI and electromagnetic compatibility problems, ground

bounce, and voltage losses. Poor layout can also affect regulation

and stability. To implement a good layout, use the following rules:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the com-

ponent side ground to further reduce noise interference on

sensitive circuit nodes.