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PRIXP425BD 数据表(PDF) 95 Page - Intel Corporation

部件名 PRIXP425BD
功能描述  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PDF  112 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

PRIXP425BD 数据表(HTML) 95 Page - Intel Corporation

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
Datasheet
95
NOTES:
1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external
device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
Table 53.
Intel Simplex Mode Values
Symbol
Parameter
Min.
Max.
Units
Notes
Taddr2valcs
Valid address to valid chip select
1
4
Cycles
1, 2, 7
Tdval2valwrt
Write data valid prior to EXPB_IO_WRITE_N falling edge
1
4
Cycles
3, 7
Twrpulse
Pulse width of the EXP_IO_WRITE_N
1
16
Cycles
4, 7
Tdholdafterwr
Valid data after the rising edge of EXPB_IO_WRITE_N
1
4
Cycles
5, 7
Trdsetup
Data valid required before the rising edge of
EXP_IO_READ_N
5.3
14.7
ns
Trdhold
Data hold required after the rising edge of
EXP_IO_READ_N
2ns
Trecov
Time required between successive accesses on the
expansion interface.
116
Cycles
6
Figure 27.
Motorola* Multiplexed Mode
A9587-01
EX_CLK
EX_ADDR
EX_DATA
EX_RD_N
(exp_mot_rnw)
EX_WR_N
(exp_mot_ds_n)
EX_DATA
EX_ALE
Valid Address
T5
1-16 Cycles
T4
1-4 Cycles
EX_CS_N
Trecov
Tale2addrhold
Tdval2valds
EX_WR_N
(exp_mot_ds_n)
EX_RD_N
(exp_mot_rnw)
Tdhold2afterds
T3
1-16 Cycles
T2
1-4 Cycles
T1
2-5 Cycles
ALE Extended
Talepulse Tale2valcs
Tdspulse
Address
Output Data
Address
Input Data
Multiplexed Address/Data
Trdsetup
Trdhold



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