95

ICs

■Pin Assignment

■Internal Block Diagram

–

+

SenseB

SenseA

12

34

5

67

89 16 10 15

11

20 21 22 23

14

MIC

15

17

12

19

18

Protect

Sequencer

&

Sleep Circuit

Pre-

Driver

OSC

PWM

Control

Synchro

Control

OSC

DAC

DAC

PWM

Control

Protect

Reg

Pre-

Driver

The protect circuit is deleted and the flag pin is N.C. for SLA7070MR, 7071MR, 7072MR, and 7073MR.

*1: N.C. pin for SLA7070MR, 7071MR, 7072MR, and 7073MR.

■Typical Connection Diagram

OutB

OutA

OutA

VDD

C1

r1

Q1

SLA7070M Series

(2-phase/1-2 phase

excitation)

Reset

Clock

CW/CCW

M1

M2

M3

Sync

N.C.

Flag

Ref/Sleep1

OutB

CA

Vs=10V to 44V

+

BB

SenseA

Gnd

One-point

Gnd

C2

Logic Gnd

CB

+

Power Gnd

r2

r3

SenseB

Vcc=3.0V to 5.5V

Micro-

computer,

etc.

* There is no Flag pin (Pin-18) for SLA7070MR, 7071MR, 7072MR, and 7073MR.

■External Dimensions (ZIP23 with Fin[SLA23Pin])

0.65

22

× 3.8

+0.2

–0.1

0.55

+0.2

–0.1

(Measured at the tip)

(Measured at

the root)

(Including the resin burr)

4–(R1)

R-end

φ

φ

Gate burr

Forming No. No.2151

Pin No.

Symbol

Function

OutA

OutA/

SenseA

N.C.

M1

M2

M3

Clock

Gnd

Ref/Sleep1

Reset

CW/CCW

Sync

SenseB

OutB/

OutB

Phase A output

Phase A output

Phase A current sense

N.C.

Excitation mode/Sleep 2 setting input

Step Clock input

Driver supply (motor supply)

Device GND

Control current mode/Sleep 1 setting input

Logic supply

Internal logic reset input

Normal/reverse control input

PWM control signal input

Phase B current sense

Phase B current output

Phase B current output

Product Mass : Approx.6g

SLA7070MR, MPR, MPRT/7071MR, MPR, MPRT/7072MR, MPR, MPRT/7073MR, MPR, MPRT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23