Datasheet

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TSZ02201-0RFR1G200450-1-2

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4.Dec.2013 Rev.001

TSZ22111･15･001

BU7250G

BU7250SG

BU7253F

BU7253SF

Operational Notes – continued

12.

Regarding the Input Pin of the IC

In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The

operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical

damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an

input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when

no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins

have voltages within the values specified in the electrical characteristics of this IC.

13.

Unused Circuits

When there are unused comparators, it is recommended that they are

connected as in Figure 45, setting the non-inverting input terminal to a

14.

Input Voltage

Applying VDD +0.3V to the input terminal is possible without causing

deterioration of the electrical characteristics or destruction, regardless of

the supply voltage. However, this does not ensure normal circuit

operation. Please note that the circuit operates normally only when the

input voltage is within the common mode input voltage range of the

electric characteristics.

15.

Power Supply(single/dual)

The voltage comparator operates when the voltage supplied is between VDD and VSS. Therefore, the single supply

voltage comparator can be used as dual supply voltage comparator as well.

16.

Output Capacitor

If a large capacitor is connected between the output pin and VSS pin, current from the charged capacitor will flow into

the output pin and may destroy the IC when the VDD pin is shorted to ground or pulled down to 0V. Use a capacitor

smaller than 0.1µF between output pin and VSS pin.

17.

Oscillation by Output Capacitor

Please pay attention to the oscillation by output capacitor and in designing an application of negative feedback loop

circuit with these ICs.

18.

Latch up

Be careful of input voltage that exceed the VDD and VSS. When CMOS device have sometimes occur latch up and

protect the IC from abnormaly noise.

19.

Open Drain Output

Please connect and use a pull-up resistor to the output since this IC has an open-drain output.

VSS

VDD

Figure 45. Example of Application Circuit

for Unused Comparator