AD5171BRJ50-R2 datasheet(7/24 Pages) AD

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AD5171

Rev. D | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

W 1

VDD 2

GND 3

SCL 4

AD0

SDA

AD5171

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

Wiper Terminal W. GND ≤ VW ≤ VDD.

VDD

Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be within

the 4.75 V and 5.25 V range and capable of driving 100 mA.

GND

Common Ground.

SCL

Serial Clock Input. Requires a pull-up resistor. If it is driven direct from a logic controller without the pull-up

resistor, ensure that the VIH minimum is 0.7 V × VDD.

SDA

Serial Data Input/Output. Requires a pull-up resistor. If it is driven direct from a logic controller without a pull-up

resistor, ensure that the VIH minimum is 0.7 V × VDD.

AD0

I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed.

Resistor Terminal B. GND ≤ VB ≤ VDD.

Resistor Terminal A. GND ≤ VA ≤ VDD.

AD5171BRJ50-R2 数据表(PDF) 7 Page - Analog Devices