R5F564MLHDLC datasheet(39/67 Pages) RENESAS

39 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 39 of 67

Feb 28, 2014

Note 1. The 176-pin LFBGA does not include the E5 pin.

Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is

enabled.

R11

VCC

R12

P80

EDREQ0

MTIOC3B/PO26

SCK10/RTS10#/

ET0_TX_EN/

RMII0_TXD_EN

MMC_D2-A/

SDHI_WP-A/

QIO2-A

R13

P76

CS6#

PO22

RXD11/ET0_RX_CLK/

REF50CK0

MMC_CMD-A/

SDHI_CMD-A/

QSSL-A

R14

P74

A20/CS4#

PO19

CTS11#/ET0_ERXD1/

RMII0_RXD1

R15

PC1

A17

MTIOC3A/TCLKD/

PO18

SCK5/SSLA2-A/

ET0_ERXD2

IRQ12

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (7/7)

Number

Power Supply

Clock System

Control

I/O Port

Bus

EXDMAC

SDRAMC

Timer

Communication

Memory Interface

Camera Interface

Interrupt

S12ADC,

R12DA

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, GPTA, TPU,

TMR, PPG, RTC,

CMTW, POE, CAC)

(ETHERC, SCIg,

SCIh, RSPI, RIIC,

CAN, USB, SSI)

(QSPI, SDHI,

MMCIF, PDC)

R5F564MLHDLC 数据表(PDF) 39 Page - Renesas Technology Corp

R5F564MLHDLC 数据表(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载