FEDL9098B-01

ML9098B

7/15

*2) Do the followings to operate the power-on reset circuit properly:

- Make a slope of a rise time of VCC/VDD equal to or smaller than 28.7V/ms.

- Connect a smoothing capacitor of 1000 pF

20% or more between the VDD pin and GND.

*3) f = 4.194304 MHz, open inputs, and non-loaded outputs.

POWER-ON/OFF TIMING

• Connect VDD and VCC pins externally to provide the equal potential.

• To prevent IC erroneous operation, keep the power ON/OFF timing.

VDD, VCC pin voltage

BIAS pin voltage (1/2Duty)

t

 0

[Voltage]

[Time]

t

t