L8565

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

2 of 13

www.unisonic.com.tw

QW-R114-004.d

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PIN CONFIGURATION

GND

1

FREQ

GATE

2

3

4

5

6

7

8

Figure 1. Pin Configuration (top view)

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PIN DESCRIPTION

PIN NO.

PIN NAME

DESCRIPTION

1

The output bus voltage of the boost converter is sensed at this pin via a resistive divider.

The reference voltage for this pin is 5V.

2

compensation network to ground (see Figure 2). This also gives the soft start function

which controls an increasing AC input current during start-up.

3

At this pin the compensation components of the current loop are connected. The

capacitor which is connected at this pin integrates the output current of OTA2 and

averages the current sense signal.

4

FREQ

A resistor connected to this pin sets the fixed switching frequency. The frequency range

is from 50kHz to 250kHz.

5

The pin senses the negative voltage drop at the external sense resistor (R1). This is the

input signal for the average current regulation in the current loop. It is also fed to the

peak current limitation block. During power up time, high inrush currents cause high

voltage drop at R1, driving currents into pin 5 which could be beyond the absolute

maximum ratings. Therefore a series resistor (R2) of around 220Ω is recommended in

order to limit this current into the IC.

6

GND

This is the Ground pin.

7

GATE

The GATE pin is the output of the internal driver stage, which has a capability of 1.5A

source and sink current. Its gate drive voltage is clamped at 11.5V (typically).

8

auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is

at 11.2V and under voltage occurs at 10.2V.