CCVGA7C9

Preliminary

TVS

UNISONICTECHNOLOGIESCO.,LTD

2 of 6

www.unisonic.com.tw

QW-R223-015.a

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PIN CONFIGURATION

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PIN DESCRIPTION

PIN NO.

PIN NAME

DESCRIPTION

1

This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their

associated ESD protection circuits.

2

This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection

circuits.

3

VIDEO_1

Video signal ESD protection channel. This pin is typically tied one of the video lines

between the VGA controller device and the video connector.

4

VIDEO_2

5

VIDEO_3

6

GND

Ground.

7

This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates.

8

BYP

This input is Using a 0.2uF bypass capacitor will increase the ESD robustness of the

system.

9

DDC_OUT1

DDC signal output. Connects to the video connector side of one of the sync lines

10

DDC_IN1

DDC signal input. Connects to the VGA controller side of one of the sync lines.

11

DDC_IN2

12

DDC_OUT2

DDC signal output. Connects to the video connector side of one of the sync lines.

13

SYNC_IN1

Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.

14

SYNC_OUT1

Sync signal buffer output. Connects to the video connector side of one of the sync lines.

15

SYNC_IN2

Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.

16

SYNC_OUT2

Sync signal buffer output. Connects to the video connector side of one of the sync lines.