Typical Performance Characteristics

6

Package Pin Description

PACKAGE PIN #

PIN SYMBOL

FUNCTION

Block Diagram

3.1V

DISABLE

FF Discharge

50µA

VREF = 3.3V

OSC

S

R

Q

150ns

Blank

13.5V

SS

PGnd

GATE

COMP

I

SET

SYNC

OV

ENABLE

FF

Latching

Discharge

1V

UV Monitor

2V

UVL

2mA(maximum load current)

Low

Sat

Gate

Driver

Thermal

Shutdown

+

-

EAMP

G

3

G4

OV Monitor

Max SS

Det

(Sat Sense)

3.0V

UV

PWM

Comp

UV Lockout

Start/Stop

G1

3.3V

5µA

SS to 1.8V Max

(Sat Sense)

Max Duty Cycle

3.0V

LGnd

2V to 1V Trip Points

Q

(1.263V)

Soft Start Clamp

ON

G2

16L PDIP & 16L SO Narrow

1

GATE

External power switch driver with 1.0A peak capability. Rail to

rail output occurs when the capacitive load is between 470pF

and 10nF.

Current sense comparator input.

3

SYNC

Bidirectional synchronization. Locks to highest frequency.

4

FF

PWM ramp.

5

UV

Undervoltage protection monitor.

6

OV

Overvoltage protection monitor.

Voltage at this pin sets pulse-by-pulse overcurrent threshold.

Feedback voltage input. Connected to the error amplifier

inverting input.

10

COMP

Error amplifier output.

11

SS

Charging external capacitor restricts error amplifier output

voltage during the power up or fault conditions.

12

LGnd

Logic Ground.

13

3.3V reference voltage output. Decoupling capacitor can be

selected from 0.01µF to 10µF.

14

Logic supply voltage.

15

PGnd

Output power stage ground.

16

Output power stage supply voltage.