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CS22250 数据表(PDF) 2 Page - Cirrus Logic

部件名 CS22250
功能描述  WIRELESS 10BT CONTROLLER
PDF  32 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS22250 数据表(HTML) 2 Page - Cirrus Logic

  CS22250 Datasheet HTML 1Page - Cirrus Logic CS22250 Datasheet HTML 2Page - Cirrus Logic CS22250 Datasheet HTML 3Page - Cirrus Logic CS22250 Datasheet HTML 4Page - Cirrus Logic CS22250 Datasheet HTML 5Page - Cirrus Logic CS22250 Datasheet HTML 6Page - Cirrus Logic CS22250 Datasheet HTML 7Page - Cirrus Logic CS22250 Datasheet HTML 8Page - Cirrus Logic CS22250 Datasheet HTML 9Page - Cirrus Logic Next Button
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CS22250 Wireless 10BT Controller
2 of 32
DS551PP2
Rev. 3.0
www.cirrus.com
2
Features
Embedded ARM Core and System Support Logic
High Performance ARM7TDMI RISC processor core up to 77MHz
4KB integrated, one-way set associative, unified, write through cache
Individual interrupt for each functional block
Two 23-bit programmable (periodic or one-shot) general purpose timers
8 Dword (32-bits) memory write and read buffers for high system performance
Abort cycle detection and reporting for debugging
ARM performance monitoring function for system fine-tuning
Programmable performance improvement logic based on system configuration.
Enhanced Memory Controller Unit
Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM/Flash
interface
16-bit data bus with 12-bit address supporting up to 4MB and up to 103 MHz (100/133MHz
SDRAM)
8-bit data bus with addressing support up to 1MB of boot ROM/Flash
Programmable SDRAM timing and size parameters, such as CAS latencies and number of
banks, columns and rows
Flexible independent DMA engines for Ethernet MAC, Digital Radio and External Bus
functional units
FEC codec
High performance Reed-Solomon coding for error correction (255:239 block coding)
Reduces error probability of a typical 10e-3 error rate environment to 10e-9
Programmable rate FEC engine to optimize channel efficiency
Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single
cycle throughput up to 77MHz, with a sustain rate of 77MBps
Double buffering (63 Dword read/write buffer) to enhance system performance
Digital Wireless Radio MAC
Glue-less interface to 802.11b radio baseband transceiver
11Mbps data rate
32 Dword transmit/receive FIFO
Supports clear channel assessment (CCA)
Ethernet Interface
IEEE802.3 Ethernet MAC controller
Two independent full-duplex DMA channels transfer between Ethernet interface to system
memory
Standard 7-pin serial interfaces to AUI or Twisted Pair 10-BaseT
Standard half-duplex CSMA/CD and full-duplex operation
USB Device Configuration Interface
USB 1.1 compliant



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