CS4297A datasheet(39/52 Pages) CIRRUS

39 / 52 page

CS4297A

7. SONY/PHILIPS DIGITAL

INTERFACE (S/PDIF)

The S/PDIF digital output is used to interface the

CS4297A to consumer audio equipment external to

the PC. This output provides an interface for stor-

ing digital audio data or playing digital audio data

to digital speakers. Figure 20 illustrates the circuits

necessary for implementing the IEC-958 optical or

consumer interface. For further information on

S/PDIF operation see application note AN22: Over-

view of Digital Audio Interface Data Structures [3].

For further information on S/PDIF recommended

transformers see application note AN134: AES and

S/PDIF Recommended Transformers [4].

8. GROUNDING AND LAYOUT

Figure 21 on page 40 shows the conceptual layout

for the CS4297A. The decoupling capacitors

should be located physically as close to the pins as

possible. Also note the connection of the REFFLT

decoupling capacitors to the ground return trace

connected directly to the ground return pin, AVss1.

It is strongly recommended that separate analog

and digital ground planes be used. Separate ground

planes keep digital noise and return currents from

modulating the CS4297A ground potential and de-

grading performance. The digital ground pins

should be connected to the digital ground plane and

kept separate from the analog ground connections

of the CS4297A and any other external analog cir-

cuitry. All analog components and traces should be

located over the analog ground plane and all digital

components and traces should be located over the

digital ground plane.

The common connection point between the two

ground planes (required to maintain a common

ground voltage potential) should be located under

the CS4297A. The AC-link digital interface con-

nection traces should be routed such that the digital

ground plane lies underneath these signals (on the

internal ground layer). This applies along the entire

length of these traces from the AC ’97 controller to

the CS4297A.

Refer to the Application Note AN18: Layout and

Design Rules for Data Converters and Other

Mixed Signal Devices [2] for more information on

layout and design rules.

0.1

µF

DGND

DVdd

SPDO/SDO2

S/PDIF_OUT

TOTX-173

SPDO/SDO2

+5V_PCI

DGND

8.2 k

Ω

DGND

3.3V

247.5

Ω

107.6

Ω

375

Ω

93.75

Ω

Figure 20. S/PDIF Output

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