CS4298 datasheet(13/52 Pages) CIRRUS

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CS4298

DS315PP2

3. DIGITAL SECTION

3.1

AC-Link

All communication with the Codec is estab-

lished with a 5-wire digital interface to the Con-

troller chip as shown in Figure 7. All clocking

for the serial communication is synchronous to

the BIT_CLK signal. BIT_CLK is generated by

the primary Codec and is used to slave the Con-

troller and any secondary Codecs, if applicable.

An AC-link audio frame is a sequence of 256 se-

rial bits organized into 13 groups referred to as

‘slots’. One frame consists of one 16-bit slot and

twelve 20-bit slots. During each audio frame,

data is passed bi-directionally between the Co-

dec and the Controller. The input frame is driv-

en from the Codec on the SDATA_IN line. The

output frame is driven from the Controller SDATA_OUT line. Both input and output frames contain

the same number of bits and are organized with the same ‘slot’ configuration. The input and output

frame have differing functions for each slot. The Controller synchronizes the beginning of a frame

with the SYNC signal. In Figure 9 the position of each bit location within the frame is noted. The

first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is

F255. When SYNC goes active (high) and is sampled active by the CS4298 (on the falling edge of

BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT

pin at this clock edge is the final bit of the previous frame’s serial data. On the next rising edge of

BIT_CLK, the first bit of Slot 0 is driven by the Controller on the SDATA_OUT pin. The CS4298

latches in this data, as the first bit of the frame, on the next falling edge of the BIT_CLK clock signal.

The Controller is also responsible for issuing reset via the RESET# signal. After being reset, the Co-

dec is responsible for flagging the Controller that it is ready for operation after synchronizing its in-

ternal functions. The AC-link signals may be referenced to either 5 Volts or 3.3 Volts. The CS4298

must use the same digital supply voltage as the Controller chip.

3.2

Control registers

All read accesses to the Codec are generated by requesting a register address (index number) in slot

1 of a SDATA_OUT frame. The following SDATA_IN frame will contain the register content in its

slot 2. The write operation is identical with the index in slot 1 and the write data in slot 2. The AC ‘97

Frame Definition section details the function of each input and output frame. Individual register de-

scriptions are found in the Register Interface section.

AC-97 Register Interface

The CS4298 implements the AC ’97 Registers in accordance with the AC ’97 2.0 Specification. See

the Register Interface section for details on the CS4298’s register set.

CODEC

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC’97

Controller

Figure 7. AC-link Connections

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