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CS42L50 数据表(PDF) 41 Page - Cirrus Logic |
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CS42L50 数据表(HTML) 41 Page - Cirrus Logic |
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41 / 48 page ![]() CS42L50 DS544PP1 41 LR C K SC L K Le ft C h an n e l R ight C h a nne l SD A T A +3 +2 +1 LS B +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 LS B +5 +4 MSB -1 -2 -3 -4 Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK. Figure 25. Left Justified, up to 24-bit data LRCK SCLK L e ft C h a nnel R ig h t C h ann el SDATA 65 4 3210 987 15 14 13 12 11 10 6543 21 0 987 15 14 13 12 11 10 3 2 c lo cks Right Justified, 16-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 32 Cycles per LRCK Period. Figure 26. Right Justified, 16-bit data LRCK SCLK Left C h ann el SDATA 6543 210 7 23 22 21 20 19 18 6 543 210 7 23 22 21 20 19 18 32 c lo cks 0 R igh t C h annel Right Justified, 24-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 48 Cycles per LRCK Period. Figure 27. Right Justified, 24-bit data |
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