CS43L42 datasheet(13/40 Pages) CIRRUS

13 / 40 page

CS43L42

DS481PP2

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA = 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL =30 pF)

Notes: 15. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

16. Data must be held for sufficient time to bridge the transition time of CCLK.

17. For FSCK < 1 MHz

Parameter

Symbol

Min

Max

Unit

SPI Mode

CCLK Clock Frequency

fsclk

-6

MHz

RST Rising Edge to CS Falling

tsrs

500

CCLK Edge to CS Falling

(Note 15)

tspi

500

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 16)

tdh

Rise Time of CCLK and CDIN

(Note 17)

tr2

-100

Fall Time of CCLK and CDIN

(Note 17)

tf2

-100

t r2

t f2

t dsu t dh

t sch

t scl

CC L K

CD IN

t css

t csh

t spi

t srs

RST

Figure 5. Control Port Timing - SPI Mode

CS43L42 数据表(PDF) 13 Page - Cirrus Logic

CS43L42 数据表(HTML) 13 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载