4

AT25DF161

Figure 2-1.

Pin Configurations

3.

Block Diagram

Figure 3-1.

Block Diagram

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF161 can be erased in four levels of granularity including

a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be

individually protected from program and erase operations. The size of the physical sectors is optimized for both code and

data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory

Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.

HOLD

SCK

SI (SIO)

2

1

8-SOIC

Top View

CS

SO (SOI)

WP

GND

8-UDFN

5

6

7

8

4

3

HOLD

SCK

SI (SIO)

2

1

Top View

CS

SO (SOI)

WP

GND

5

6

7

8

4

3

CS

SCK

SI (SIO)

SO (SOI)

WP

HOLD

INTERFACE

CONTROL

AND

LOGIC

CONTROL AND

PROTECTION LOGIC

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

Y-DECODER

X-DECODER

3687H–DFLASH–5/2013