CS4812 datasheet(21/36 Pages) CIRRUS

21 / 36 page

CS4812

DS291PP3

and a memory address pointer (MAP) byte. The

MAP byte contains the address of the control port

the host controller sends the actual data byte to be

written to the register designated by the MAP. The

host controller then de-asserts CS. Figure 16 shows

the SPI slave mode write flow diagram.

In SPI slave mode, a read sequence from an exter-

nal controller is shown in Figure 17. The host con-

troller executes a partial write-cycle by sending a

16-bit write preamble to the CS4812 with the MAP

byte set to the address of the control port byte reg-

ister to be read. The host controller then de-asserts

CS, re-asserts CS, and sends the 7-bit chip address

followed by the R/W bit set to 1. The host control-

ler then clocks out the control port register desig-

nated by the MAP byte. The host controller then

de-asserts CS. Figure 18 shows the SPI mode slave

read flow diagram initiated by the host microcon-

troller. Figure 19 shows the SPI slave mode read

flow diagram incorporating the DSP REQ signal.

REQ is used to notify the host controller that a data

byte from the DSP is waiting to be read.

The behavior of the REQ signal is dependent on

when data is written to the serial control port output

byte being transferred. There are three cases of

REQ behavior:

1. The REQ line will be de-asserted immediately

following the rising edge of CCLK on the D2 bit of

the current byte being transferred if there is no data

in the serial control port output register. The REQ

line remains de-asserted and a stop condition

SET CS LOW

WRITE DATA BYTE

MORE DATA?

SET CS HIGH

WRITE MAP BYTE

WRITE ADDRESS BYTE

WITH R/W BIT = 0

Figure 16. SPI Slave Write Flow Diagram

CDOUT

CLK

CDIN

10 11 12

CHIP ADDRESS (WRITE)

MAP BYTE

MSB

R/W

CHIP ADDRESS (READ)

R/W

0 INCR 6

REQ

13 14 15

DATA

(input)

(output)

(input)

(output)

DATA

Figure 17. Control Port Timing, SPI Slave Mode Read

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