CS49312 datasheet(39/86 Pages) CIRRUS

39 / 86 page

CS49300 Family DSP

DS339PP4

The timing diagram in Figure 24, "I2C® Timing"

on page 40 shows the relative edges of the control

lines for an I2C® read and write.

6.1.3. INTREQ Behavior: A Special Case

When communicating with the CS493XX there are

two types of messages which force INTREQ to go

low. These messages are known as solicited

messages and unsolicited messages. For more

information on the specific types of messages that

require a read from the host, one of the application

code user’s guides should be referenced.

general,

when

communicating

with

the

CS493XX, INTREQ will not go low unless the

host first sends a read request command message.

In other words the host must solicit a response from

the DSP. In this environment, the host must read

from the CS493XX until INTREQ goes high again.

Once the INTREQ pin has gone high it will not be

driven low until the host sends another read

request.

When unsolicited messages, such as those used for

Autodetect, have been enabled, the behavior of

INTREQ is noticeably different. The CS493XX

will drop the INTREQ pin whenever the DSP has

an outgoing message, even though the host may not

have requested data.

There are three ways in which INTREQ can be

affected by an unsolicited message:

1) During normal operation, while INTREQ is

high, the DSP could drop INTREQ to indicate an

outgoing message, without a prior read request.

2) The host is in the process of reading from the

CS493XX, meaning that INTREQ is already low.

An unsolicited message arrives which forces

INTREQ to remain low after the solicited message

is read.

3) The host is reading from the CS493XX when the

unsolicited message is queued, but INTREQ goes

high for one period of SCCLK and then goes low

again before the end of the read cycle.

In case (1) the host should perform a read operation

as discussed in the previous sections.

In case (2) an unsolicited message arrives before

the second to last SCCLK of the final byte transfer

of a read, forcing the INTREQ pin to remain low.

In this scenario the host should continue to read

from the CS493XX without a stop/start condition

or data will be lost.

In case (3) an unsolicited message arrives between

the second to last SCCLK and the last SCCLK of

the final byte transfer of a read. In this scenario,

INTREQ will transition high for one clock (as if the

read transaction has ended), and then back low

(indicating that more data has queued). This final

case is the most complicated and shall be explained

in detail.

There are two constraints which completely

characterize the behavior of the INTREQ pin

during a read. The first constraint is that the

INTREQ pin is guaranteed to remain low until the

second to last SCCLK (SCCLK number N-1) of the

final byte being transferred from the CS493XX

(not necessarily the second to last bit of the data

byte). The second constraint is that once the

INTREQ pin has gone high it is guaranteed to

remain high until the rising edge of the last SCCLK

(SCCLK number N) of the final byte being

transferred from the CS493XX (not necessarily the

last bit of the data byte). If an unsolicited message

arrives in the window of time between the rising

edge of the second to last SCCLK and the final

SCCLK, INTREQ will drop low on the rising edge

of the final SCCLK as illustrated in the functional

timing diagrams shown for I2C® and SPI read

cycles.

INTREQ behavior for I2C® communication is

illustrated in Figure 24, "I2C® Timing" on page

40. When using I2C® communication the INTREQ

pin will remain low until the rising edge of SCCLK

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